Wireless infrastructure applications require high frequency, low phase noise, clock signals to drive various components in wireless transceivers such as, for example, Digital-Analog-Converters (DACs), Analog-Digital-Converters (ADCs), and other clock generators such as Local Oscillator (LO) generators.
To obtain a high frequency output clock signal to drive various components, typically a low frequency reference clock signal is multiplied up to the high frequency by using an integer-N phase-locked loop (PLL), where N is the amount by which the reference clock signal is multiplied.
FIG. 1 shows a conventional integer-N PLL-based clock generator 102. The clock generator 102 includes a reference clock 104 which generates a reference clock signal FREF, a phase frequency detector (PFD) 106, a charge pump (CP) 108, a loop filter (LF) 110, a voltage controlled oscillator (VCO) 112 which generates an output clock signal FOUT, and a frequency divider (DIV-N) 114. The frequency divider 114 outputs the comparison clock signal FDIV, which is the FOUT signal divided by N (the amount by which the reference clock signal FREF is to be multiplied). The reference clock signal FREF and the comparison signal FDIV are both input into the PFD 106. For each clock cycle of the reference clock signal FREF, if the PFD 106 detects a phase difference and/or a frequency difference between FREF and FDIV, the PFD sends a pulse signal PS to the CP 108. Upon receipt of the pulse signal PS, the CP 108 generates a corresponding control current IC. The LF 110 converts the control current IC to a control voltage VC. The control voltage VC controls the frequency of the output clock signal FOUT generated by the VCO 112. The output clock signal FOUT from the VCO is proportional to the control voltage VC. The output clock signal FOUT is used by various other components in wireless transceivers as their input clock.
As noted above, the output clock signal FOUT is divided down by the frequency divider 116 by a factor of N to generate the comparison clock signal FDIV. The comparison clock signal FDIV is compared to the reference clock signal FREF in the PFD 106 to, ultimately, control the VCO 112. With a negative feedback loop as described above, the PLL-based frequency synthesizer multiplies the reference clock signal FREF by N amount, wherein N is an integer, while locking output clock signal FOUT from the VCO 112 to the phase and frequency of the reference clock signal FREF.
When a reference clock signal is multiplied up to a higher frequency using a conventional integer-N PLL-based clock generator 102 as shown in FIG. 1, spurious content is generated in the high frequency output clock signal. The spurious content comes from leakage of the reference clock signal and its harmonics into the output clock signal. Specifically, the spurious content is caused by the phase frequency detector 106 and charge pump 108. Phase frequency detectors and charge pumps need to be large and of high voltage to control the high voltage VCOs which produce the high quality output clock signals. These large, high voltage, phase frequency detectors and charge pumps, however, cause significant power supply transients in the surrounding circuitry and introduce disturbances during each phase detection and charge pump event (i.e. each clock cycle of the reference clock signal). Both the charging activity and the parasitic coupling between charge pump circuitry and output path circuitry (e.g. shared ground) generate unwanted spurious content on the higher frequency output clock signals. The result is that a spike of spurious content is generated in the output clock signal once in every N of its cycles—the spike corresponding in time to, and caused by the circuit activity triggered by, the clock edge of the reference clock signal.
To limit the deleterious effect of spurious content in wireless transceiver components which use the output clock signal, reference clocks above 100 MHz are currently used. This results in spurious content at least 100 MHz away from the output clock signal. This is preferred since it does not negatively affect the components in wireless transceivers to the same extent as does spurious content less than 100 MHz away. Next generation systems are using 300 MHz and even 600 MHz reference clock signals to further distance the spurious content from the output clock signal (push the spurious content out of band). A drawback to using high frequency reference clocks, however, is the cost. Reference clocks below 30-40 MHz are generally quite cost optimized. Another drawback is that the phase frequency detectors and charge pumps must be faster to accommodate the high frequency reference clock signals.